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NXP Semiconductors /LPC5410x /ASYNCSYSCON /ASYNCAPBCLKCTRL

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Interpret as ASYNCAPBCLKCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED 0 (USART0)USART0 0 (USART1)USART1 0 (USART2)USART2 0 (USART3)USART3 0 (I2C0)I2C0 0 (I2C1)I2C1 0 (I2C2)I2C2 0RESERVED 0 (SPI0)SPI0 0 (SPI1)SPI1 0RESERVED 0 (TIMER0)TIMER0 0 (TIMER1)TIMER1 0 (FRG0)FRG0 0RESERVED

Description

Async peripheral clock control

Fields

RESERVED

Reserved. Read value is undefined, only zero should be written.
USART0

Controls the clock for USART0. 0 = Disable; 1 = Enable.
USART1

Controls the clock for USART1. 0 = Disable; 1 = Enable.
USART2

Controls the clock for USART2. 0 = Disable; 1 = Enable.
USART3

Controls the clock for USART3. 0 = Disable; 1 = Enable.
I2C0

Controls the clock for I2C0. 0 = Disable; 1 = Enable.
I2C1

Controls the clock for I2C1. 0 = Disable; 1 = Enable.
I2C2

Controls the clock for I2C2. 0 = Disable; 1 = Enable.
RESERVED

Reserved. Read value is undefined, only zero should be written.
SPI0

Controls the clock for SPI0. 0 = Disable; 1 = Enable.
SPI1

Controls the clock for SPI1. 0 = Disable; 1 = Enable.
RESERVED

Reserved. Read value is undefined, only zero should be written.
TIMER0

Controls the clock for TIMER0. 0 = Disable; 1 = Enable.
TIMER1

Controls the clock for TIMER1. 0 = Disable; 1 = Enable.
FRG0

Controls the clock for the Fractional Rate Generator used with the USARTs. 0 = Disable; 1 = Enable.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data